Principal Soc Rtl Engineer

Company Overview Ambiq &nbsp;is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions. Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 290 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications. Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology. We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency. At Ambiq, we live by five values:&nbsp; Innovate. Collaborate. Focus. Learn. Achieve. If that's you, join us — the intelligence everywhere revolution starts here. &nbsp; We’re looking for a&nbsp; Principal RTL Engineer &nbsp;to own pre-tapeout quality for digital SoC modules on our MCU platforms and drive architecture, microarchitecture, and RTL development for next-generation silicon. In this role, you’ll develop&nbsp; Verilog/SystemVerilog RTL &nbsp;for complex IPs and SoCs, evaluate and integrate&nbsp; 3rd-party IP , partner closely with&nbsp; verification and FPGA teams &nbsp;on test planning and debug, collaborate with&nbsp; physical design &nbsp;to hit timing and power targets, and drive&nbsp; LINT, CDC, RDC, silicon bring-up, and validation &nbsp;quality. This is a&nbsp; hands-on principal IC role &nbsp;for an engineer who has built and debugged complex SoCs, knows how to raise quality before tapeout, and wants direct impact on production silicon. Responsibilities Own and be responsible for pre-tape out quality for digital SOC modules on the MCU Explore architecture and develop micro-architecture. RTL development for IPs and SOCs using Verilog 3rd party IP identification, selection, and integration Collaboration with verification and FPGA teams in test plan development and debug Collaborate with the Physical Design team to close the design on timing and power targets Assist in silicon bring-up and validation; Run tool for quality checks (LINT, CDC, and RDC) and fix/waive the issues Requirements <div class="" data-automation-id="job-requiremen